On the optimum checkpoint selection problem
SIAM Journal on Computing
High-Performance Fault-Tolerant VLSI Systems Using Micro Rollback
IEEE Transactions on Computers
High-level synthesis: introduction to chip and system design
High-level synthesis: introduction to chip and system design
Optimal VLSI architectural synthesis: area, performance and testability
Optimal VLSI architectural synthesis: area, performance and testability
High-level synthesis of fault-secure microarchitectures
DAC '93 Proceedings of the 30th international Design Automation Conference
Synthesis of fault-tolerant and real-time microarchitectures
Journal of Systems and Software - Special issue on fault tolerance in real-time systems
Microarchitectural synthesis of VLSI designs with high test concurrency
DAC '94 Proceedings of the 31st annual Design Automation Conference
Rapid prototyping of fault-tolerant VLSI systems
ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
IEEE Design & Test
Microarchitectural Synthesis of Performance-Constrained, Low-Power VLSI Designs
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
Derivation and Calibration of a Transient Error Reliability Model
IEEE Transactions on Computers
ACM Transactions on Embedded Computing Systems (TECS)
| Hi-index | 0.00 |
The growing trend towards VLSI implementation Of crucial tasks in critical applications has increased both the demand for and the scope of fault-tolerant VLSI systems. In this paper, we present a self-recovering microarchitecture synthesis system. In a self-recovering microarchitecture, intermediate results are compared at regular intervals, and if correct saved in registers (checkpointing). On the other hand, on detecting a fault, the self-recovering microarchitecture rolls back to a previous checkpoint and retries. The proposed synthesis system comprises of a heuristic and an optimal subsystem. The heuristic synthesis subsystem has two components. Whereas the checkpoint insertion algorithm identifies good checkpoints by successively eliminating clock cycle boundaries that either have a high checkpoint overhead or violate the retry period constraint, the novel edge-bused scheduler assigns edges to clock cycle boundaries, in addition to scheduling nodes to clock cycles. Also, checkpoint insertion and edge-based scheduling are intertwined using a flexible synthesis methodology. We additionally show an Integer Linear Programming model for the self-recovering microarchitecture synthesis problem. The resulting ILP formulation can minimize either the number of voters or the overall hardware, subject to constraints on the number of clock cycles, the retry period, and the number of checkpoints.