High-Level Synthesis of Recoverable Microarchitectures

Authors:
Seong Y. Ohm;Douglas M. Blough;Fadi J. Kurdahi
Affiliations:
Department of Electrical & Computer Science, University of California, Irvine, CA;Department of Electrical & Computer Science, University of California, Irvine, CA;Department of Electrical & Computer Science, University of California, Irvine, CA
Venue:
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Year:
1996

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Abstract

Two algorithms that combine the operations of scheduling and recovery point insertion for high-level synthesis of recoverable microarchitectures are presented. The first uses a prioritized cost function in which functional unit cost is minimized first and register cost second. The second algorithm minimizes a weighted sum of functional unit and register costs. Both algorithms are optimal according to their respective cost functions and require less than 10 minutes of CPU time on widely-used high-level synthesis benchmarks. The best previous result reported several hours of CPU time for some of the same benchmarks.