Energy Aware Computing through Probabilistic Switching: A Study of Limits
IEEE Transactions on Computers
Multi-media Applications and Imprecise Computation
DSD '05 Proceedings of the 8th Euromicro Conference on Digital System Design
A case study in reliability-aware design: a resilient LDPC code decoder
Proceedings of the conference on Design, automation and test in Europe
A reconfigurable ASIP for convolutional and turbo decoding in an SDR environment
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Design of voltage overscaled low-power trellis decoders in presence of process variations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Error-resilient low-power Viterbi decoder architectures
IEEE Transactions on Signal Processing
Scalable effort hardware design: exploiting algorithmic resilience for energy efficiency
Proceedings of the 47th Design Automation Conference
Proceedings of the 47th Design Automation Conference
A rapid prototyping system for error-resilient multi-processor systems-on-chip
Proceedings of the Conference on Design, Automation and Test in Europe
ERSA: error resilient system architecture for probabilistic applications
Proceedings of the Conference on Design, Automation and Test in Europe
Designing Chips without Guarantees
IEEE Design & Test
Reliable on-chip systems in the nano-era: lessons learnt and future trends
Proceedings of the 50th Annual Design Automation Conference
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Reliability is the next big challenge if CMOS scaling will continue. To face this challenge, cross-layer approaches become mandatory. In this paper we present a dynamic error detection and correction flow for wireless communication. We demonstrate this flow on a flexible state-of-the-art decoder, i.e., an HSPA/LTE channel decoder. A profound analysis of the impact of timing and soft errors on the system behavior is presented. Dynamic techniques utilizing higher layers of communication systems to compensate these errors are proposed. This approach results in very low overhead for error resilience.