Design of voltage overscaled low-power trellis decoders in presence of process variations

Authors:
Yang Liu;Tong Zhang;Jiang Hu
Affiliations:
Department of Electrical, Computer, and Systems Engineering, Rensselaer Polytechnic Institute Troy, NY;Department of Electrical, Computer, and Systems Engineering, Rensselaer Polytechnic Institute Troy, NY;Department of Electrical and Computer Engineering, Texas A&M University, College Station, TX
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2009

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Abstract

In hardware implementations of many signal processing functions, timing errors on different circuit signals may have largely different importance with respect to the overall signal processing performance. This motivates us to apply the concept of unequal error tolerance to enable the use of voltage overscaling at minimal signal processing performance degradation. Realization of unequal error tolerance involves two main issues, including how to quantify the importance of each circuit signal and how to incorporate the importance quantification into signal processing circuit design. We developed techniques to tackle these two issues and applied them to two types of trellis decoders including Viterbi decoder for convolutional code decoding and Max-Log-Maximum A Posteriori (MAP) decoder for Turbo code decoding. Simulation results demonstrated promising energy saving potentials of the proposed design solution on both trellis decoding computation and memory storage at small decoding performance degradation.