Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Parameter variations and impact on circuits and microarchitecture
Proceedings of the 40th annual Design Automation Conference
VLSI Implementation of low-power high-quality color interpolation processor for CCD camera
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Demosaicing: image reconstruction from color CCD samples
IEEE Transactions on Image Processing
Color plane interpolation using alternating projections
IEEE Transactions on Image Processing
Design of voltage overscaled low-power trellis decoders in presence of process variations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
ColSpace: towards algorithm/implementation co-optimization
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
HERQULES: system level cross-layer design exploration for efficient energy-quality trade-offs
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
Process-variation resilient and voltage scalable DCT architecture for robust low-power computing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Exploring the fidelity-efficiency design space using imprecise arithmetic
Proceedings of the 16th Asia and South Pacific Design Automation Conference
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Power dissipation and tolerance to process variations pose conflicting design requirements. Scaling of voltage is associated with larger variations, while Vdd up-scaling or transistor up-sizing for process tolerance can be detrimental for power dissipation. However, for certain signal processing systems such as those used in color image processing, we noted that effective trade-offs can be achieved between Vdd scaling, process tolerance and "output quality". In this paper we demonstrate how these tradeoffs can be effectively utilized in the development of novel low-power variation tolerant architectures for color interpolation. The proposed architecture supports a graceful degradation in the PSNR (Peak Signal to Noise Ratio) under aggressive voltage scaling as well as extreme process variations in sub-70nm technologies. This is achieved by exploiting the fact that some computations are more important and contribute more to the PSNR improvement compared to the others. The computations are mapped to the hardware in such a way that only the less important computations are affected by Vdd-scaling and process variations. Simulation results show that even at a scaled voltage of 60% of nominal Vdd value, our design provides reasonable image PSNR with 69% power savings.