The Enterprise Model for Developing Distributed Applications
IEEE Parallel & Distributed Technology: Systems & Technology
SPARK: A High-Lev l Synthesis Framework For Applying Parallelizing Compiler Transformations
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Task Graph Extraction for Embedded System Synthesis
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Displaying dependence graphs: a hierarchical approach
WCRE '01 Proceedings of the Eighth Working Conference on Reverse Engineering (WCRE'01)
System Design Using Kahn Process Networks: The Compaan/Laura Approach
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Symbolic noise analysis approach to computational hardware optimization
Proceedings of the 45th annual Design Automation Conference
Exploring the fidelity-efficiency design space using imprecise arithmetic
Proceedings of the 16th Asia and South Pacific Design Automation Conference
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Application-specific integrated circuits (ASICs) are physical implementations of algorithms, so implementation metrics are determined in large part by the algorithm specification. However, the system abstraction layers that have been developed to manage the ever-increasing complexity of digital systems separate algorithm designers from hardware designers, forcing the latter to work within the design space specified by the former, even for applications such as multimedia that do not have hard fidelity requirements. Designers typically employ informal iterative design to adjust fidelity, but a formal design methodology would increase designer efficiency and improve the quality of the solutions. This paper introduces such a methodology (and accompanying tool) that enables algorithm and implementation metrics to be co-optimized during early design exploration, opening the design space to include solutions that may provide, for example, significant performance improvements while only slightly compromising fidelity. Hierarchical dependency graphs (HDGs) are used to represent both the algorithm and the implementation architecture, providing a common interface through which algorithm designers and hardware designers can explore the collaborative space (ColSpace) together. Using the proposed technique, the ColSpace tool can trade off various metrics to find the best overall design while managing complexity with the HDG hierarchy. Two image processing case studies demonstrate that in ColSpace-optimized designs, latency savings can exceed fidelity losses, resulting in cost function reductions that would not have been possible without this co-optimization methodology.