Task Graph Extraction for Embedded System Synthesis

  • Authors:
  • Keith S. Vallerio;Niraj K. Jha

  • Affiliations:
  • -;-

  • Venue:
  • VLSID '03 Proceedings of the 16th International Conference on VLSI Design
  • Year:
  • 2003

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Abstract

Consumer demand and improvements in hardware havecaused distributed real-time embedded systems to rapidly increasein complexity. As a result, designers faced with time-to-market constraints are forced to rely on intelligent designtools to enable them to keep up with demand. These tools arecontinually being used earlier in the design process whenthe design is at higher levels of abstraction. At the highestlevel of abstraction are hardware/software co-synthesis toolswhich take a system specification as input. Although manyembedded systems are described in C, the system specificationsfor many of these tools are often in the form of one ormore task graphs. These tools are very effective at solvingthe co-synthesis problem using task graphs but require thatdesigners manually transform the specification from C codeto task graphs, a tedious and error-prone job. The task graphextraction tool described in this paper reduces the potentialfor error and the time required to design an embedded systemby automating the task graph extraction process. Sucha tool can drastically improve designer productivity. As faras we know, this is the first tool of its kind. It has been madeavailable on the web.