Time Redundancy Based Soft-Error Tolerance to Rescue Nanometer Technologies
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
A Highly-Efficient Technique for Reducing Soft Errors in Static CMOS Circuits
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
Analysis of Error Recovery Schemes for Networks on Chips
IEEE Design & Test
Low complexity LDPC code decoders for next generation standards
Proceedings of the conference on Design, automation and test in Europe
Joint consideration of fault-tolerance, energy-efficiency and performance in on-chip networks
Proceedings of the conference on Design, automation and test in Europe
A rapid prototyping system for error-resilient multi-processor systems-on-chip
Proceedings of the Conference on Design, Automation and Test in Europe
ERSA: error resilient system architecture for probabilistic applications
Proceedings of the Conference on Design, Automation and Test in Europe
Design and architectures for dependable embedded systems
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
A case study on error resilient architectures for wireless communication
ARCS'12 Proceedings of the 25th international conference on Architecture of Computing Systems
Reliable on-chip systems in the nano-era: lessons learnt and future trends
Proceedings of the 50th Annual Design Automation Conference
A hybrid HW-SW approach for intermittent error mitigation in streaming-based embedded systems
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
ACM Transactions on Embedded Computing Systems (TECS) - Special Section on ESTIMedia'10
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Chip reliability becomes a great threat to the design of future microelectronic systems with the continuation of the progressive downscaling of CMOS technologies. Hence increasing the robustness of chip implementations in terms of error tolerance becomes an important issue. In this paper we present a case study in reliability-aware design tolerating transient errors. A state-of-the-art WiMAX channel decoder for LDPC codes is investigated on all design levels to increase its reliability for a given system performance with minimum hardware overhead. We show that an efficient exploitation of the algorithmic fault-tolerance yields a fairly small area overhead with nearly no degradation in communications performance even under high error injection rates.