Hardware/Software Trade-Offs for Advanced 3G Channel Coding
Proceedings of the conference on Design, automation and test in Europe
Implementation of a UMTS Turbo-Decoder on a Dynamically Reconfigurable Platform
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Channel Decoder Architecture for 3G Mobile Wireless Terminals
Proceedings of the conference on Design, automation and test in Europe - Volume 3
A multi-standard channel-decoder for base-station applications
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
Design and Analysis of a Programmable Single-Chip Architecture for DVB-T Base-Band Receiver
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
ASIP-based multiprocessor SoC design for simple and double binary turbo decoding
Proceedings of the conference on Design, automation and test in Europe: Proceedings
SODA: A Low-power Architecture For Software Radio
Proceedings of the 33rd annual international symposium on Computer Architecture
New Schemes in Clustered VLIW Processors Applied to Turbo Decoding
ASAP '06 Proceedings of the IEEE 17th International Conference on Application-specific Systems, Architectures and Processors
Scalable reconfigurable channel decoder architecture for future wireless handsets
Proceedings of the conference on Design, automation and test in Europe
Flexible LDPC decoder architectures
VLSI Design - Special issue on Flexible Radio Design: Trends and Challenges in Digital Baseband Implementation
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Future mobile and wireless communication networks require flexible modem architectures to support seamless services between different network standards. Hence, a common hardware platform that can support multiple protocols implemented or controlled by software, generally referred to as software defined radio (SDR), is essential. This paper presents a family of dynamically reconfigurable application-specific instruction-set processors (ASIP) for the application domain of channel coding in wireless communication systems. As a weakly programmable IP core, it can implement trellis based channel decoding in a SDR environment. It features binary convolutional decoding, and turbo decoding for binary as well as duobinary turbo codes for all current and upcoming standards. The ASIPs consist of a specialized pipeline with 15 stages and a dedicated communication and memory infrastructure. Logic synthesis revealed a maximum clock frequency of 400 MHz and a total area of 0.42 mm2 for a 65 nm technology. Simulation results for Viterbi and turbo decoding demonstrate maximum throughput of 196 and 34 Mbps, respectively, and outperforms existing SDR based approaches for channel decoding.