Channel Decoder Architecture for 3G Mobile Wireless Terminals
Proceedings of the conference on Design, automation and test in Europe - Volume 3
Proceedings of the conference on Design, automation and test in Europe
A reconfigurable ASIP for convolutional and turbo decoding in an SDR environment
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In this paper, a VLSI implementation of a multi-standard channel-decoder for EDGE, WCDMA, and CDMA2k convolutional-codes is presented. The new architecture employs the MAP algorithm for convolutional decoding to support soft-outputs.The decoder is designed for base-station applications. The maximum throughput of the decoder is 16 Mbps for WCDMA and CDMA2k, and 70 Mbps for EDGE, at a clock frequency of 200 MHz.