High-speed VLSI architectures for soft-output Viterbi decoding
Journal of VLSI Signal Processing Systems - Special issue on application specific array processors (ASAP-92)
Low power implementation of a turbo-decoder on programmable architectures
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
A multi-standard channel-decoder for base-station applications
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
Scalable reconfigurable channel decoder architecture for future wireless handsets
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the conference on Design, automation and test in Europe
A reconfigurable ASIP for convolutional and turbo decoding in an SDR environment
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Architecture of run-time reconfigurable channel decoder
ICC'09 Proceedings of the 2009 IEEE international conference on Communications
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Channel coding is a key element of any digital wireless communication system since it minimizes the effects of noise and interference on the transmitted signal. In third-generation (3G) wireless systems channel coding techniques must serve both voice and data users whose requirements considerably vary. Thus the Third Generation Partnership Project (3GPP) standard offers two coding techniques, convolutional-coding for voice and Turbo-coding for data services. In this paper we present a combined channel decoding architecture for 3G terminal applications. It outperforms a solution based on two separate decoders due to an ef.cient reuse of computational hardware and memory resources for both decoders. Moreover it supports blind transport format detection. Special emphasis is put on low energy consumption.