Low power implementation of a turbo-decoder on programmable architectures

  • Authors:
  • Frank Gilbert;Alexander Worm;Norbert Wehn

  • Affiliations:
  • Institute of Microelectronic Systems, Department of Electrical Engineering and Information Technology, University of Kaiserslautern;Institute of Microelectronic Systems, Department of Electrical Engineering and Information Technology, University of Kaiserslautern;Institute of Microelectronic Systems, Department of Electrical Engineering and Information Technology, University of Kaiserslautern

  • Venue:
  • Proceedings of the 2001 Asia and South Pacific Design Automation Conference
  • Year:
  • 2001

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Abstract

Low Power is an extremely important issue for future mobile radio systems. Channel decoders are essential building blocks of base-band signal processing units in mobile terminal architectures. Thus low power implementations of advanced channel decoding techniques are mandatory. In this paper we present a low power implementation of the most sophisticated channel decoding algorithm (Turbo-decoding) on programmable architectures. Low power optimization is performed on two abstraction levels: on system level by the use of an intelligent cancellation technique, on implementation level by the use of dynamic voltage scaling. With these techniques we can reduce the worst case is also applicable for hardware implementations. To the best of our knowledge, this is the first in-depth study of low power implementations of Turbo-decoders based on voltage scheduling for third generation wireless systems.