ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Energy efficient data transfer and storage organization for a MAP turbo decoder module
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Low power implementation of a turbo-decoder on programmable architectures
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Energy efficient turbo decoding for 3G mobile
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Low Power Digital CMOS Design
Vlsi Architectures For High-Speed Map Decoders
VLSID '01 Proceedings of the The 14th International Conference on VLSI Design (VLSID '01)
Hi-index | 0.01 |
The outstanding forward error correction provided by Turbo-Codes made them part of today's and emerging communications standards. Therefore, efficient Turbo-Decoder architectures are important building blocks in communications systems. In this paper we present a scalable, highly parallel architecture for UMTS compliant Turbo decoding and apply architecture-driven voltage scaling to reduce the energy consumption. We will show that this approach adds some additional, more energy-efficient solutions to the design space of low power Turbo decoding systems. It can save up to 34% of the decoding energy per datablock under realistic voltage assumptions. We present throughput, area, and energy results for various degrees of parallelization based on synthesis on a 0.18 μm ASIC-technology library, which is characterized for two different supply voltages: nominal 1.8 V and nominal 1.3 V.