VLSI architectures for SISO-APP decoders
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
VLSI Architectural design tradeoffs for sliding-window Log-MAP decoders
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Architecture-driven voltage scaling for high-throughput turbo-decoders
Journal of Embedded Computing - Low-power Embedded Systems
VLSI architectures for sliding-window-based space-time turbo trellis code decoders
Journal of Electrical and Computer Engineering - Special issue on Implementations of Signal-Processing Algorithms for OFDM Systems
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Soft-in/soft-out building blocks are becoming increasingly important in present and future communication systems, as they enable better communications performance. The maximum a posteriori (MAP) algorithm is the best known soft-in/soft-out decoder. Its performance is superior to the soft-out Viterbi algorithm (SOVA). However, optimized high-speed MAP decoder implementation is widely unexplored. We present a novel VLSI high-speed MAP architecture with optimized memory size and power consumption suitable for decoding the revolutionary "Turbo-Codes" and related concatenation schemes. The architecture is highly scalable with respect to throughput, expanding its applicability over a wide range of throughput requirements (300 Mbit/s-45 Gbit/s and above). An in-depth design space exploration on multiple abstraction levels has been carried out. Area and power consumption are significantly reduced, compared to the state-of-the-art.