VLSI architectures for sliding-window-based space-time turbo trellis code decoders

Authors:
Georgios Passas;Steven Freear
Affiliations:
School of Electronic and Electrical Engineering, University of Leeds, Leeds, UK;School of Electronic and Electrical Engineering, University of Leeds, Leeds, UK
Venue:
Journal of Electrical and Computer Engineering - Special issue on Implementations of Signal-Processing Algorithms for OFDM Systems
Year:
2012

Citing 9
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Abstract

The VLSI implementation of SISO-MAP decoders used for traditional iterative turbo coding has been investigated in the literature. In this paper, a complete architectural model of a space-time turbo code receiver that includes elementary decoders is presented. These architectures are based on newly proposed building blocks such as a recursive add-compare-select-offset (ACSO) unit, A-, B-, Γ-, and LLR output calculation modules. Measurements of complexity and decoding delay of several sliding-windowtechnique-based MAP decoder architectures and a proposed parameter set lead to defining equations and comparison between those architectures.