Logic synthesis
Figures of merit to characterize the importance of on-chip inductance
DAC '98 Proceedings of the 35th annual Design Automation Conference
Getting to the bottom of deep submicron II: a global wiring paradigm
ISPD '99 Proceedings of the 1999 international symposium on Physical design
Algorithms for VLSI Physical Design Automation
Algorithms for VLSI Physical Design Automation
Clock rate versus IPC: the end of the road for conventional microarchitectures
Proceedings of the 27th annual international symposium on Computer architecture
Compiler Support for Scalable and Efficient Memory Systems
IEEE Transactions on Computers
The optimal logic depth per pipeline stage is 6 to 8 FO4 inverter delays
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
A scalable instruction queue design using dependence chains
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Latency-guided on-chip bus network design
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Behavior Analysis of Internal Feedback Bridging Faults in CMOS Circuits
Journal of Electronic Testing: Theory and Applications
Coping with Latency in SOC Design
IEEE Micro
Very Large Scale Spatial Computing
UMC '02 Proceedings of the Third International Conference on Unconventional Models of Computation
Molecular electronics: devices, systems and tools for gigagate, gigabit chips
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
A clock-tuning circuit for system-on-chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Enabling on-chip diversity through architectural communication design
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
A Scalable System Architecture for High-Throughput Turbo-Decoders
Journal of VLSI Signal Processing Systems
Hybrid CMOS/nanoelectronic digital circuits: devices, architectures, and design automation
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Architecture-driven voltage scaling for high-throughput turbo-decoders
Journal of Embedded Computing - Low-power Embedded Systems
| Hi-index | 4.11 |
Several independent sources forecast that in deep-submicron (DSM) process geometries, 80 percent or more of the delays of critical paths will be directly linked to interconnect. This forecast is supported by the significant timing-closure problems that are arising in current high-performance IC designs. Based on this, both industry and academia sense the need for a significant over-haul of current synthesis and physical-design methodologies. In the emerging design scenario, traditional design flows will no longer be viable for any size of module or block of gates. Deep-submicron effects-particularly those relating to interconnects-have thus been billed as potential roadblocks to the continuation of Moore's law. Some effects, like the rising resistance-capacitance (RC) delay of on-chip wiring, noise considerations, reliability concerns, and increased power dissipation, manifest themselves in both the devices (transistors) and the interconnect, though not in ways previously anticipated. The authors consider the effects of both devices and interconnect. Their analysis shows that interconnect delay actually decreases for DSM processes in a modular design approach. The physical explanations of these DSM effects shed insight into this and other potential impacts on future high-performance ASIC designs.