A clock-tuning circuit for system-on-chip

Authors:
Yaron Elboim;Avinoam Kolodny;Ran Ginosar
Affiliations:
Intel Corporation, Haifa 31015, Israel;Electrical Engineering Department, Technion-Israel Institute of Technology, Haifa 32000, Israel;Very Large Scale Integration (VLSI) Systems Research Center, Electrical Engineering Department, Technion-Israel Institute of Technology, Haifa 32000, Israel
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2003

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Abstract

System-on-chip (SoC) design depends heavily on effective reuse of semiconductor intellectual property (IP). Clock distribution has become a problem for integrating IP cores into a single synchronous SoC, because of different clock delays in the IP cores. We propose an onchip clock-tuning circuit, which enhances design flexibility. Programmable delays are inserted in the clock distribution network, such that clock alignment and synchronization are achieved. Design iterations are eliminated with the use of the tuning circuit, saving design effort, and cost. The method is also applicable to compensating for unbalanced clock trees. Hierarchical clock tuning can be implemented and can take advantage of the hierarchical structure of the SoC. Skew analysis has shown that the added programming unit outperforms other clock design options. The method was implemented in a commercial chip, and demonstrated good functionality with high productivity of the design flow.