Testing interconnects for noise and skew in gigahertz SoCs
Proceedings of the IEEE International Test Conference 2001
A Multi-PLL Clock Distribution Architecture for Gigascale Integration
WVLSI '01 Proceedings of the IEEE Computer Society Workshop on VLSI 2001
A clock-tuning circuit for system-on-chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low Cost Scheme for On-Line Clock Skew Compensation
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
A novel clock distribution and dynamic de-skewing methodology
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Skew measurements in clock distribution circuits using an analytic signal method
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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We present a low-cost on-line system for clock skew management in integrated circuits. Our Built-In Clock Skew System (BICSS) uses a centralized approach to identify, quantify and correct skew using a two-step method. The technique assesses the time-of-flight between the central debug circuitry and each region, or tap under test to account for the measurement error due to differences in path length common in existing techniques. The system can be used to detect skew above a user-adjustable margin using a variable tolerance phase detector. The result is a solution which provides silicon debug and repair capability of on-chip clock skews with a very small area overhead.