Let's route packets instead of wires
AUSCRYPT '90 Proceedings of the sixth MIT conference on Advanced research in VLSI
HSRA: high-speed, hierarchical synchronous reconfigurable array
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Tolerating operational faults in cluster-based FPGAs
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
NanoFabrics: spatial computing using molecular electronics
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
VPR: A new packing, placement and routing tool for FPGA research
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
Defect tolerance on the Teramac custom computer
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
WHICH CONCURRENT ERROR DETECTION SCHEME TO CHOOSE?
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Nanowire-based sublithographic programmable logic arrays
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Design of programmable interconnect for sublithographic programmable logic arrays
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
Neuromorphic architectures for nanoelectronic circuits: Research Articles
International Journal of Circuit Theory and Applications - Nanoelectric Circuits
Seven Strategies for Tolerating Highly Defective Fabrication
IEEE Design & Test
A Reconfiguration-Based Defect-Tolerant Design Paradigm for Nanotechnologies
IEEE Design & Test
Defect tolerance at the end of the roadmap
Nano, quantum and molecular computing
Law of large numbers system design
Nano, quantum and molecular computing
CMOL crossnets as pattern classifiers
IWANN'05 Proceedings of the 8th international conference on Artificial Neural Networks: computational Intelligence and Bioinspired Systems
Single-walled carbon nanotube electronics
IEEE Transactions on Nanotechnology
Stochastic assembly of sublithographic nanoscale interfaces
IEEE Transactions on Nanotechnology
Structures and electrical properties of Ag-tetracyanoquinodimethane organometallic nanowires
IEEE Transactions on Nanotechnology
Logic synthesis of multilevel circuits with concurrent error detection
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Performance-driven mapping for CPLD architectures
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A reconfigurable architecture for hybrid CMOS/Nanodevice circuits
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
On the use of Bloom filters for defect maps in nanocomputing
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Combining static and dynamic defect-tolerance techniques for nanoscale memory systems
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
CMOL: Second life for silicon?
Microelectronics Journal
Reconfigurable RTD-based circuit elements of complete logic functionality
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
MBARC: a scalable memory based reconfigurable computing framework for nanoscale devices
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
SAT-based equivalence checking of threshold logic designs for nanotechnologies
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Design and defect tolerance beyond CMOS
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
Emerging nanodevice paradigm: Graphene-based electronics for nanoscale computing
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Evolution in architectures and programming methodologies of coarse-grained reconfigurable computing
Microprocessors & Microsystems
Complete nanowire crossbar framework optimized for the multi-spacer patterning technique
CASES '09 Proceedings of the 2009 international conference on Compilers, architecture, and synthesis for embedded systems
Routing congestion removing of CMOL FPGA circuits by a recursive method
MINO'10 Proceedings of the 9th WSEAS international conference on Microelectronics, nanoelectronics, optoelectronics
Defect-aware logic mapping for nanowire-based programmable logic arrays via satisfiability
Proceedings of the Conference on Design, Automation and Test in Europe
Computing with nanoscale memory: Model and architecture
NANOARCH '09 Proceedings of the 2009 IEEE/ACM International Symposium on Nanoscale Architectures
History index of correct computation for fault-tolerant nano-computing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Defect-Aware Nanocrossbar Logic Mapping through Matrix Canonization Using Two-Dimensional Radix Sort
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Scaling-efficient in-situ training of CMOL CrossNet classifiers
Neural Networks
Learning with memristive devices: How should we model their behavior?
NANOARCH '11 Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures
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Physics offers several active devices with nanometer-scale footprint, that can be best used in combination with a CMOS subsystem. Such hybrid circuits offer the potential for high defect tolerance combined with unparalleled performance. In this tutorial, we highlight key issues and architectural alternatives for this promising technology and outline the challenges posed by the hybrid circuits pose for design automation.