Hybrid CMOS/nanoelectronic digital circuits: devices, architectures, and design automation
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Radial addressing of nanowires
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Microelectronic Engineering
Decoding nanowire arrays fabricated with the multi-spacer patterning technique
Proceedings of the 46th Annual Design Automation Conference
Stochastic assembly of sublithographic nanoscale interfaces
IEEE Transactions on Nanotechnology
Assembling nanoscale circuits with randomized connections
IEEE Transactions on Nanotechnology
Variability-Aware Design of Multilevel Logic Decoders for Nanoscale Crossbar Memories
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Nanowire crossbar circuits are an emerging architectural paradigm that promises a higher integration density and an improved fault-tolerance due to its reconfigurability. In this paper, we propose for the first time the utilization of the multi-spacer patterning technique to fabricate nanowire crossbars with a high cross-point density up to 1010 cm(-2). We propose a novel decoder fabrication method that can be included in a process dedicated to the multi-spacer patterning technique. We address the technology problems consisting in the variability and fabrication complexity at the design level by optimizing the encoding scheme. We show an overall reduction of the variability by 18% and a cancelation of the fabrication complexity overhead.