Design of programmable interconnect for sublithographic programmable logic arrays
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
Radial addressing of nanowires
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Microelectronic Engineering
Stochastic assembly of sublithographic nanoscale interfaces
IEEE Transactions on Nanotechnology
Assembling nanoscale circuits with randomized connections
IEEE Transactions on Nanotechnology
Variability-Aware Design of Multilevel Logic Decoders for Nanoscale Crossbar Memories
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Complete nanowire crossbar framework optimized for the multi-spacer patterning technique
CASES '09 Proceedings of the 2009 international conference on Compilers, architecture, and synthesis for embedded systems
NanoV: nanowire-based VLSI design
Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures
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Silicon nanowires are a promising solution to address the increasing challenges of fabrication and design at the future nodes of the Complementary Metal-Oxide-Semiconductor (CMOS) Technology roadmap. Despite the attractive opportunity that offers their organization onto regular crossbars, the problem of designing the nano-wire decoder is still challenging and highly dependent on the nanowire fabrication technology. In this paper, we introduce a novel design style and encoding scheme for decoding nanowires fabricated with the Multi-Spacer-Patterning Technique (MSPT); and we present a method based on Gray codes that reduces the fabrication cost and improves the decoder reliability. We show that by arranging the code in a Gray code fashion, we decrease the fabrication complexity by 17% and the variability by 18% on average. By optimizing the decoder parameters, the simulations showed an improvement of the crossbar yield by 40% and a reduction of the effective bit area by 51% to 169 nm2.