PathFinder: a negotiation-based performance-driven router for FPGAs
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
FPGA routing architecture: segmentation and buffering to optimize speed and density
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
NanoFabrics: spatial computing using molecular electronics
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
Minimizing FPGA Interconnect Delays
IEEE Design & Test
VPR: A new packing, placement and routing tool for FPGA research
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
Molecular electronics: devices, systems and tools for gigagate, gigabit chips
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Reconfigurable Architectures for General-Purpose Computing
Reconfigurable Architectures for General-Purpose Computing
Nanowire-based sublithographic programmable logic arrays
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Law of large numbers system design
Nano, quantum and molecular computing
Array-based architecture for FET-based, nanoscale electronics
IEEE Transactions on Nanotechnology
Stochastic assembly of sublithographic nanoscale interfaces
IEEE Transactions on Nanotechnology
Performance-driven mapping for CPLD architectures
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Seven Strategies for Tolerating Highly Defective Fabrication
IEEE Design & Test
Nanowire-based programmable architectures
ACM Journal on Emerging Technologies in Computing Systems (JETC)
A reconfigurable architecture for hybrid CMOS/Nanodevice circuits
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
Hybrid CMOS/nanoelectronic digital circuits: devices, architectures, and design automation
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Automated design flow for diode-based nanofabrics
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Interactive presentation: Improving the fault tolerance of nanometric PLA designs
Proceedings of the conference on Design, automation and test in Europe
Fault-tolerant multi-level logic decoder for nanoscale crossbar memory arrays
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
CMOL: Second life for silicon?
Microelectronics Journal
FPGA Architecture: Survey and Challenges
Foundations and Trends in Electronic Design Automation
Fault tolerant nano-memory with fault secure encoder and decoder
Proceedings of the 2nd international conference on Nano-Networks
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Towards a framework for designing applications onto hybrid nano/CMOS fabrics
Microelectronics Journal
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Decoding nanowire arrays fabricated with the multi-spacer patterning technique
Proceedings of the 46th Annual Design Automation Conference
Regular 2D NASIC-based architecture and design space exploration
NANOARCH '11 Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures
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Sublithographic Programmable Logic Arrays can be interconnected and restored using nanoscale wires. Building on a hybrid of bottom-up assembly techniques supported by conventional lithographic patterning, we show how modest-sized PLA logic blocks, which are efficient for implementing logic, can be organized into a segmented, Manhattan mesh interconnection scheme. The resulting programmable architecture has a macro-scale view which is reminiscent of lithographic FPGA and CPLD designs despite the fact that the low-level, sublithographic fabrication techniques used are much more highly constrained than conventional lithography and are prone to high defect rates. Using the Toronto 20 benchmark set, we begin to explore the design space for these sublithographic architectures and show that they may allow us to exploit nanowire building blocks to reach one to two orders of magnitude greater density than 22nm CMOS lithography.