Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Functional Testing of Semiconductor Random Access Memories
ACM Computing Surveys (CSUR)
NanoFabrics: spatial computing using molecular electronics
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
Sensitivity and Optimization
Nanowire-based sublithographic programmable logic arrays
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Design of programmable interconnect for sublithographic programmable logic arrays
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
Nanowire-based programmable architectures
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Radial addressing of nanowires
ACM Journal on Emerging Technologies in Computing Systems (JETC)
High-performance CMOS variability in the 65-nm regime and beyond
IBM Journal of Research and Development - Advanced silicon technology
Fault-tolerant multi-level logic decoder for nanoscale crossbar memory arrays
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Array-based architecture for FET-based, nanoscale electronics
IEEE Transactions on Nanotechnology
Stochastic assembly of sublithographic nanoscale interfaces
IEEE Transactions on Nanotechnology
Assembling nanoscale circuits with randomized connections
IEEE Transactions on Nanotechnology
Hi-index | 0.00 |
The use of nanowire crossbars to build devices with large storage capabilities is a very promising architectural paradigm for forthcoming nanoscale memory devices. However, this new type of memory devices raises questions regarding how to test their correct operation. In particular, the variability affecting the decoder is expected to make very complex the test of these new devices. In this paper we present a method to simplify the test of these new devices by using a current thresholder to detect badly addressed nanowires. In the proposed method, the thresholder design is based on a stochastic and perturbative model of the current through the nanowires. Thus, the calculated thresholder parameters are robust against technology variation. As our experimental results indicate, the thresholder error probability is initially only ~ 10-4, which can be also reduced further (up to ~ 60x) by trading-off only ~ 35% area overhead in the memory.