PathFinder: a negotiation-based performance-driven router for FPGAs
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
TCG-S: orthogonal coupling of P*-admissible representations for general floorplans
Proceedings of the 39th annual Design Automation Conference
Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
Algorithms for VLSI Design Automation
Algorithms for VLSI Design Automation
Efficient circuit clustering for area and power reduction in FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A Probabilistic-Based Design Methodology for Nanoscale Computation
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Design of programmable interconnect for sublithographic programmable logic arrays
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
Nanowire-based programmable architectures
ACM Journal on Emerging Technologies in Computing Systems (JETC)
A reconfigurable architecture for hybrid CMOS/Nanodevice circuits
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
Interactive presentation: Improving the fault tolerance of nanometric PLA designs
Proceedings of the conference on Design, automation and test in Europe
Combining 2-level logic families in grid-based nanoscale fabrics
NANOARCH '07 Proceedings of the 2007 IEEE International Symposium on Nanoscale Architectures
Performance-driven mapping for CPLD architectures
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Defect-Aware High-Level Synthesis Targeted at Reconfigurable Nanofabrics
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Nanofabric power analysis: Biosequence alignment case study
NANOARCH '11 Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures
MDE-based FPGA physical design: fast model-driven prototyping with Smalltalk
Proceedings of the International Workshop on Smalltalk Technologies
Nanoarray architectures multilevel simulation
ACM Journal on Emerging Technologies in Computing Systems (JETC) - Special Issue on Reliability and Device Degradation in Emerging Technologies and Special Issue on WoSAR 2011
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The design of CAD tools for nanofabrics involves new challenges not encountered with conventional design flow used for CMOS technology. In this paper, we propose to define a new framework able to help the designer to map an application on a wide range of emerging nanofabrics. Our proposal is based on a variety of models that capture as well as isolate the differences between these fabrics. This tool supports the design flow starting from behavioral description up to final layout. It integrates fault-tolerant techniques and fabric-related density transformations with more conventional design automation techniques. After an overview of common requirements, physical models, and associated techniques, a case study in the context of NASIC fabrics is used to illustrate some of the concepts.