Combining 2-level logic families in grid-based nanoscale fabrics

Authors:
Teng Wang; Pritish Narayanan; Csaba Andras Moritz
Affiliations:
Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, USA;Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, USA;Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, USA
Venue:
NANOARCH '07 Proceedings of the 2007 IEEE International Symposium on Nanoscale Architectures
Year:
2007

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Abstract

Most proposed architectures for nanoscale computing systems are based on a certain type of 2-level logic family, e.g., AND-OR, NOR-NOR, etc. In this paper, we propose a new fabric architecture that combines different logic families in the same nanofabric. To achieve this we apply very minor modifications on the way a nanogrid is controlled but without changing the basic manufacturing assumptions. This new hybrid 2-level logic based fabric yields higher density for the applications mapped to it. When fault tolerance techniques are added it significantly improves fault tolerance. A nanoscale processor is implemented on this fabric for evaluation purposes. We found that compared with an implentation on a NASIC (Nanoscale Application Specific IC) fabric with one type of 2-level logic, the density of this processor improves by up to 48% by using the hybrid logic. Furthermore, the yield is improved by 22% at 5% defective transistors and by 4X at 10% defect rates. Detailed analysis on density and yield is provided. The approach is applicable in grid-based fabrics in general: e.g., it can be used in both NASIC and CMOL designs.