N3ASICs: Designing nanofabrics with fine-grained CMOS integration

Authors:
Pavan Panchapakeshan;Pritish Narayanan;Csaba Andras Moritz
Affiliations:
Electrical and Computer Engineering, University of Massachusetts, Amherst, USA;Electrical and Computer Engineering, University of Massachusetts, Amherst, USA;Electrical and Computer Engineering, University of Massachusetts, Amherst, USA
Venue:
NANOARCH '11 Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures
Year:
2011

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Abstract

We propose a novel nanofabric approach that mixes unconventional nanomanufacturing with CMOS manufacturing flow and design rules in order to build a reliable nanowire-CMOS fabric called N3ASIC with no new manufacturing constraints added. Active devices are formed on a dense uniform semiconductor nanowire array and standard area distributed pins/vias; metal interconnects route the signals in 3D. CMOS design rules are followed. Novel nanowire based devices are envisioned and characterized based on 3D physics modeling. Overall N3ASIC fabric design, associated circuits, interconnection approach, and a layer-by-layer assembly sequence for the fabric are introduced. Key system level metrics such as power, performance, and density for a nanoprocessor design built using N3ASICs were evaluated and compared against a functionally equivalent CMOS design synthesized with state-of-the-art CAD tools. We show that the N3ASICs version of the processor is 3X denser and 5X more power efficient for a comparable performance than the 16-nm scaled CMOS version even without any new/unknown-manufacturing requirement added.