CMOS Control Enabled Single-Type FET NASIC
ISVLSI '08 Proceedings of the 2008 IEEE Computer Society Annual Symposium on VLSI
Irreversibility and heat generation in the computing process
IBM Journal of Research and Development
On the physical implementation of logical transformations: Generalized L-machines
Theoretical Computer Science
Validating cascading of crossbar circuits with an integrated device-circuit exploration
NANOARCH '09 Proceedings of the 2009 IEEE/ACM International Symposium on Nanoscale Architectures
N3ASICs: Designing nanofabrics with fine-grained CMOS integration
NANOARCH '11 Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures
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Heat dissipation is a critical challenge facing nanocomputing technologies. One component of dissipative computation costs - the unavoidable cost of implementing logically irreversible operations - fixes fundamental limits on the minimum energy cost for computational strategies that utilize these ubiquitous operations. This cost contributes little to the total power budget in conventional CMOS technology, but may be of critical significance in dense nanocomputing circuits operating at high speeds. In transistor-based paradigms, dissipation costs from logical irreversibility may be supplemented by unavoidable costs associated with particle supply required to maintain the computational "working substance." This motivates determination of lower bounds on the dissipative cost of computation in concrete nanocomputing paradigms, transistor-based and otherwise. In this work, we outline a general approach for the determination of such bounds. We first sketch our general approach, and elaborate via illustrative application to a full adder circuit implemented in the transistor-based NASIC nanofabric. The resulting bound reflects fundamental minimum costs associated with irreversible information loss and electron supply that are specific to the underlying computational strategy employed by the circuit. Finally, for perspective, fundamental bounds are compared to calculated energy consumption from HSPICE simulations for the NASIC adder.