Validating cascading of crossbar circuits with an integrated device-circuit exploration
NANOARCH '09 Proceedings of the 2009 IEEE/ACM International Symposium on Nanoscale Architectures
Regular 2D NASIC-based architecture and design space exploration
NANOARCH '11 Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures
Nanoscale Application Specific Integrated Circuits
NANOARCH '11 Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures
Determining fundamental heat dissipation bounds for transistor-based nanocomputing paradigms
NANOARCH '11 Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures
Impact of nanomanufacturing flow on systematic yield losses in nanoscale fabrics
NANOARCH '11 Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures
N3ASICs: Designing nanofabrics with fine-grained CMOS integration
NANOARCH '11 Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures
Variability in Nanoscale Fabrics: Bottom-up Integrated Analysis and Mitigation
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Design investigation of nanoelectronic circuits using crossbar-based nanoarchitectures
Microelectronics Journal
Nanoarray architectures multilevel simulation
ACM Journal on Emerging Technologies in Computing Systems (JETC) - Special Issue on Reliability and Device Degradation in Emerging Technologies and Special Issue on WoSAR 2011
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A new hybrid CMOS-nanoscale circuit style has been developed that uses only one type of Field Effect Transistor (FET) in the logic portions of a design. This is enabled by CMOS providing control signals that coordinate the operation of the logic implemented in the nanoscale. In this paper, the new circuit style is explored, examples from a microprocessor design are shown, performance, manufacturing and density implications discussed. The system is based on the existing CMOS-nano hybrid fabric architecture NASIC, but the new circuit style reduces the requirements on devices and manufacturing from previous NASIC designs, significantly improves performance without any deterioration in circuit density.