A process-tolerant cache architecture for improved yield in nanoscale technologies
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Designing Memory Subsystems Resilient to Process Variations
ISVLSI '07 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
CMOS Control Enabled Single-Type FET NASIC
ISVLSI '08 Proceedings of the 2008 IEEE Computer Society Annual Symposium on VLSI
Combining 2-level logic families in grid-based nanoscale fabrics
NANOARCH '07 Proceedings of the 2007 IEEE International Symposium on Nanoscale Architectures
Validating cascading of crossbar circuits with an integrated device-circuit exploration
NANOARCH '09 Proceedings of the 2009 IEEE/ACM International Symposium on Nanoscale Architectures
Impact of nanomanufacturing flow on systematic yield losses in nanoscale fabrics
NANOARCH '11 Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures
Reconfigurable Hybrid CMOS/Nanodevice Circuits for Image Processing
IEEE Transactions on Nanotechnology
Heterogeneous Two-Level Logic and Its Density and Fault Tolerance Implications in Nanoscale Fabrics
IEEE Transactions on Nanotechnology
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Emerging nanodevice-based architectures will be impacted by parameter variation in conjunction with high defect rates. Variations in key physical parameters are caused by manufacturing imprecision as well as fundamental atomic scale randomness. In this article, the impact of parameter variation on nanoscale computing fabrics is extensively studied through a novel integrated methodology across device, circuit and architectural levels. This integrated approach enables to study in detail the impact of physical parameter variation across all fabric layers. A final contribution of the article includes novel techniques to address this impact. The variability framework, while generic, is explored extensively on the Nanoscale Application Specific Integrated Circuits (NASICs) nanowire fabric. For variation of σ = 10 in key physical parameters, the on current is found to vary by up to 3.5X. Circuit-level delay shows up to 118% deviation from nominal. Monte Carlo simulations using an architectural simulator found 67% nanoprocessor chips to operate below nominal frequencies due to variation. New built-in variation mitigation and fault-tolerance schemes, leveraging redundancy, asymmetric delay paths and biased voting schemes, were developed and evaluated to mitigate these effects. They are shown to improve performance by up to 7.5X on a nanoscale processor design with variation, and improve performance in designs relying on redundancy for defect tolerance, without variation assumed. Techniques show up to 3.8X improvement in effective-yield performance products even at a high 12% defect rate. The suite of techniques provides a design space across key system-level metrics such as performance, yield and area.