Power and performance tradeoffs with process variation resilient adaptive cache architectures
Proceedings of the 21st annual symposium on Integrated circuits and system design
Data memory subsystem resilient to process variations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ViPZonE: OS-level memory variability-driven physical address zoning for energy savings
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Variability in Nanoscale Fabrics: Bottom-up Integrated Analysis and Mitigation
ACM Journal on Emerging Technologies in Computing Systems (JETC)
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As technology scales, more sophisticated fabrication processes cause variations in many different parameters in the device. These variations could severely affect the performance of processors by making the latency of circuits less predictable and thus requiring conservative design approaches. In this paper, we use Monte-Carlo simulations in addition to worst-case circuit analysis to establish the overall delay due to process variations in a cache subsystem under both typical and worst-case conditions. The distribution of a cache critical-path-delay in the typical scenario was determined by performing Monte-Carlo simulations at different supply voltages, threshold voltages, and transistor lengths on a complete cache design. In addition to establishing the delay variation, we present an adaptive variable-cycle-latency cache architecture that mitigates the impact of process variations on access latency by closely following the typical latency behavior rather than assuming a conservative worst-case design-point. Simulation results show that our adaptive data cache can achieve a 9% to 21% performance improvement in a superscalar processor, on the SPEC2000 applications studied, compared to a conventional design. Additional performance improvement potential exists in processors where the data cache access is on the critical path, by allowing a more aggressive clock rate.