On designing via-configurable cell blocks for regular fabrics
Proceedings of the 41st annual Design Automation Conference
HARP: hard-wired routing pattern FPGAs
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
A Mask Reuse Methodology for Reducing System-on-a-Chip Cost
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
An integrated design flow for a via-configurable gate array
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Architectural implications of brick and mortar silicon manufacturing
Proceedings of the 34th annual international symposium on Computer architecture
The impact of interconnect architecture on via-programmed structured ASICs (VPSAs)
Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
Via configurable three-input lookup-tables for structured ASICs
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Power gating design for standard-cell-like structured ASICs
Proceedings of the Conference on Design, Automation and Test in Europe
Designing via-configurable logic blocks for regular fabric
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Rover: routing on via-configurable fabrics for standard-cell-like structured ASICs
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Area impact analysis of via-configurable regular fabric for digital integrated circuit design
Proceedings of the 24th symposium on Integrated circuits and systems design
N3ASICs: Designing nanofabrics with fine-grained CMOS integration
NANOARCH '11 Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures
A framework for compiler driven design space exploration for embedded system customization
ASIAN'04 Proceedings of the 9th Asian Computing Science conference on Advances in Computer Science: dedicated to Jean-Louis Lassez on the Occasion of His 5th Cycle Birthday
Standard cell like via-configurable logic blocks for structured ASIC in an industrial design flow
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design and analysis of via-configurable routing fabrics for structured ASICs
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
A regular fabric design methodology for applications requiring specific layout-level design rules
Microelectronics Journal
| Hi-index | 0.00 |
There is currently a huge gap between the two main technologiesused to implement custom digital integrated circuit (IC) designs.At one end of the spectrum are field programmable gate arrays(FPGAs). These devices have relatively low design costs and shortdesign times, but they also have high per-unit costs and arelimited interms of design size, complexity, and performance. At theother end of the device continuum are application specificintegrated circuits (ASICs). These components have exceedingly highdesign costs and take a long time to develop, but they can supportextremely large, complex,and high-performance designs, and theyhave low per-unit costs in large production runs. A new category ofdevices - known as structured ASICs - is now becoming available.These devices bridge the gap between FPGAs and ASICs in terms ofcost and capabilities, but they also pose challenges to devicemanufacturers and design tool vendors.