An architectural exploration of via patterned gate arrays
Proceedings of the 2003 international symposium on Physical design
VPR: A new packing, placement and routing tool for FPGA research
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
Exploring regular fabrics to optimize the performance-cost trade-off
Proceedings of the 40th annual Design Automation Conference
Structured ASICs: Opportunities and Challenges
ICCD '03 Proceedings of the 21st International Conference on Computer Design
Exploring Logic Block Granularity for Regular Fabrics
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Design methodology and tools for NEC electronics' structured ASIC ISSP
Proceedings of the 2004 international symposium on Physical design
Design considerations for regular fabrics
Proceedings of the 2004 international symposium on Physical design
Structured ASIC, evolution or revolution?
Proceedings of the 2004 international symposium on Physical design
Design automation for mask programmable fabrics
Proceedings of the 41st annual Design Automation Conference
Design methodology for IC manufacturability based on regular logic-bricks
Proceedings of the 42nd annual Design Automation Conference
A metal and via maskset programmable VLSI design methodology using PLAs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Via-configurable routing architectures and fast design mappability estimation for regular fabrics
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A lithography-friendly structured ASIC design approach
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Standard Cell Like Via-Configurable Logic Block for Structured ASICs
ISVLSI '08 Proceedings of the 2008 IEEE Computer Society Annual Symposium on VLSI
Designing via-configurable logic blocks for regular fabric
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
PLA-based regular structures and their synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Standard cell like via-configurable logic blocks for structured ASIC in an industrial design flow
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Architecture and design flow for a highly efficient structured ASIC
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In this article we study layout and circuit implementations of 3-input lookup table (3-LUT) for via configurable structured ASIC. We present a new 3-LUT circuit and several layout designs. We also propose a method to improve the delay of any logic function with fewer inputs. A 3-LUT, being able to realize all the 256 3-input functions, enables us to synthesize a circuit using both a standard cell synthesizer and an FPGA technology mapper such as FlowMap. Our study shows that circuits synthesized using a standard-cell synthesizer usually achieves better timing than that obtained by FlowMap. Our study further shows that the well-known 3-LUT implemented with multiplexers achieves better timing, area, and power dissipation. Our methodology can be also employed to study look-up tables with more inputs.