Via configurable three-input lookup-tables for structured ASICs
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Power gating design for standard-cell-like structured ASICs
Proceedings of the Conference on Design, Automation and Test in Europe
Rover: routing on via-configurable fabrics for standard-cell-like structured ASICs
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Transistor sizing in lithography-aware regular fabrics
Proceedings of the 24th symposium on Integrated circuits and systems design
Area impact analysis of via-configurable regular fabric for digital integrated circuit design
Proceedings of the 24th symposium on Integrated circuits and systems design
Standard cell routing via boolean satisfiability
Proceedings of the 49th Annual Design Automation Conference
Standard cell like via-configurable logic blocks for structured ASIC in an industrial design flow
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Architecture and design flow for a highly efficient structured ASIC
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Routability optimization for crossbar-switch structured ASIC design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Design and analysis of via-configurable routing fabrics for structured ASICs
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
A regular fabric design methodology for applications requiring specific layout-level design rules
Microelectronics Journal
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A structured ASIC has some arrays of pre-fabricated yet configurable logic blocks (CLBs) with/without a regular routing fabric. In this paper, we propose a standard cell like via-configurable logic block (VCLB). We design a 0.18um standard cell library based on our VCLB and establish a design flow using as many commercial tools as possible. We also propose a method to evaluate the viability of a structured ASIC fabric. Our structured ASIC fabric with programmable metals for routing achieves a delay of 2.7 times, an area of 3 times, and a power of 1.5 times that attained by the designs using a commercial cell library.