Embedded tutorial: subwavelength lithography
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
IC design in high-cost nanometer-technologies era
Proceedings of the 38th annual Design Automation Conference
An architectural exploration of via patterned gate arrays
Proceedings of the 2003 international symposium on Physical design
Synthesis and placement flow for gain-based programmable regular fabrics
Proceedings of the 2003 international symposium on Physical design
VPR: A new packing, placement and routing tool for FPGA research
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
Exploring regular fabrics to optimize the performance-cost trade-off
Proceedings of the 40th annual Design Automation Conference
Structured ASICs: Opportunities and Challenges
ICCD '03 Proceedings of the 21st International Conference on Computer Design
Exploring Logic Block Granularity for Regular Fabrics
Proceedings of the conference on Design, automation and test in Europe - Volume 1
CMOS Structures Suitable for Secured Hardware
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Structured ASIC, evolution or revolution?
Proceedings of the 2004 international symposium on Physical design
Enabling energy efficiency in via-patterned gate array devices
Proceedings of the 41st annual Design Automation Conference
Heterogeneous Programmable Logic Block Architectures
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Design methodology for IC manufacturability based on regular logic-bricks
Proceedings of the 42nd annual Design Automation Conference
A metal and via maskset programmable VLSI design methodology using PLAs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Via-configurable routing architectures and fast design mappability estimation for regular fabrics
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A lithography-friendly structured ASIC design approach
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Standard Cell Like Via-Configurable Logic Block for Structured ASICs
ISVLSI '08 Proceedings of the 2008 IEEE Computer Society Annual Symposium on VLSI
A comparison of via-programmable gate array logic cell circuits
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Rapid prototyping on a structured ASIC fabric
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Soft Errors in Modern Electronic Systems
Soft Errors in Modern Electronic Systems
Selectively patterned masks: structured ASIC with asymptotically ASIC performance
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Designing via-configurable logic blocks for regular fabric
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
PLA-based regular structures and their synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Measuring the Gap Between FPGAs and ASICs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Performance and Cost Tradeoffs in Metal-Programmable Structured ASICs (MPSAs)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Standard cell like via-configurable logic blocks for structured ASIC in an industrial design flow
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Regular fabrics have been introduced as an approach to bridge the gap between ASICs and FPGAs in terms of cost and performance. Indeed, compared to an ASIC, by predefining most of the manufacturing masks, they highly reduce time-to-market, non-recoverable engineering costs and lithography hazards. Also, thanks to hardwired configuration and interconnections their performance is closer to those of ASICs than those of FPGAs. They are therefore well suited to many applications requiring low to medium volume applications or higher performance than those provided by FPGAs. In this paper, we evaluate the interest of using a regular fabric to reduce time and design cost significantly in applications involving specific transistor level design (radiative/spacial conditions, side-channel attacks, NMR environment, etc.). With this aim in view, after a broad state of the art overview with an emphasis on architectures and design flows, we develop our approach of a regular fabric designed to limit layout level design, ad-hoc tools and technological migration cost. Then, we evaluate its performance in a 65 nm process versus FPGA and standard cell based ASIC implementations. For sequential designs, our proposed solution is on average 2.5xslower and 2.3xbigger than a standard cell implantation, but also on average 13xfaster than a FPGA.