Minimum Energy Near-threshold Network of PLA based Design
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
A design flow to optimize circuit delay by using standard cells and PLAs
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
A PLA based asynchronous micropipelining approach for subthreshold circuit design
Proceedings of the 43rd annual Design Automation Conference
Structured and tuned array generation (STAG) for high-performance random logic
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Pipelined network of PLA based circuit design
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Via configurable three-input lookup-tables for structured ASICs
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Power gating design for standard-cell-like structured ASICs
Proceedings of the Conference on Design, Automation and Test in Europe
Area impact analysis of via-configurable regular fabric for digital integrated circuit design
Proceedings of the 24th symposium on Integrated circuits and systems design
Standard cell like via-configurable logic blocks for structured ASIC in an industrial design flow
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A regular fabric design methodology for applications requiring specific layout-level design rules
Microelectronics Journal
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Two regular circuit structures based on the programmable logic array (PLA) are proposed. They provide alternatives to the widely used standard-cell structure and have better predictability and simpler design methodologies. A whirlpool PLA is a cyclic four-level structure, which has a compact layout. Doppio-ESPRESSO, a four-level logic minimization algorithm, is developed for the synthesis of Whirlpool PLAs. A river PLA is a stack of multiple output PLAs, which uses river routing for the interconnections of the adjacent PLAs. A synthesis algorithm for river PLAs uses multilevel logic synthesis, simulated-annealing, and ESPRESSO targeting a combination of minimal area and delay.