Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
BooleDozer: logic synthesis for ASICs
IBM Journal of Research and Development
Recent progress in unconstrained nonlinear optimization without derivatives
Mathematical Programming: Series A and B - Special issue: papers from ismp97, the 16th international symposium on mathematical programming, Lausanne EPFL
“Timing closure by design,” a high frequency microprocessor design methodology
Proceedings of the 37th Annual Design Automation Conference
IC design in high-cost nanometer-technologies era
Proceedings of the 38th annual Design Automation Conference
A semi-custom design flow in high-performance microprocessor design
Proceedings of the 38th annual Design Automation Conference
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
Analysis of blocking dynamic circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Backend CAD flows for "restrictive design rules"
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
A design flow to optimize circuit delay by using standard cells and PLAs
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Circuit architecture for low-power race-free programmable logic arrays
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
The circuit and physical design of the POWER4 microprocessor
IBM Journal of Research and Development
PLA-based regular structures and their synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Regularly structured design techniques can combat complexity on a variety of fronts. We present the Structured and Tuned Array Generation (STAG) design methodology, which provides a complete design solution from logic to layout for regularly structured circuits. The STAG circuit tuning constraints are a key component of the methodology. The tuning contraints first guide a SPICE-level tuner to a violation free region in the design space. Secondly, the tuning methodology provides flexibility for targeting a variety of design contraints and objectives. Design examples illustrate STAG's ability for fast turnaround time as well as for high performance and timing critical random logic.