The road to better reliability and yield embedded DFM tools
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Hierarchical dummy fill for process uniformity
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Introduction to VLSI Systems
Death, taxes and failing chips
Proceedings of the 40th annual Design Automation Conference
Optical proximity correction (OPC): friendly maze routing
Proceedings of the 41st annual Design Automation Conference
Technology migration technique for designs with strong RET-driven layout restrictions
Proceedings of the 2005 international symposium on Physical design
RADAR: RET-aware detailed routing using fast lithography simulations
Proceedings of the 42nd annual Design Automation Conference
Structured and tuned array generation (STAG) for high-performance random logic
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Technology migration techniques for simplified layouts with restrictive design rules
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Variability and yield improvement: rules, models, and characterization
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Exact combinatorial optimization methods for physical design of regular logic bricks
Proceedings of the 44th annual Design Automation Conference
Characterizing process variation in nanometer CMOS
Proceedings of the 44th annual Design Automation Conference
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Manufacturability-Aware Design of Standard Cells
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Statistical design of the 6T SRAM bit cell
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Transistor sizing in lithography-aware regular fabrics
Proceedings of the 24th symposium on Integrated circuits and systems design
Leakage reduction through optimization of regular layout parameters
Microelectronics Journal
Automatic design rule correction in presence of multiple grids and track patterns
Proceedings of the 50th Annual Design Automation Conference
Standard cell like via-configurable logic blocks for structured ASIC in an industrial design flow
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design and analysis of via-configurable routing fabrics for structured ASICs
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
| Hi-index | 0.00 |
To meet challenges of deep-subwavelength technologies (particularly 130 nm and following), lithography has come to rely increasingly on data processes such as shape fill, optical proximity correction, and RETs like altPSM. For emerging technologies (65 nm and following) the computation cost and complexity of these techniques are themselves becoming bottlenecks in the design-silicon flow. This has motivated the recent calls for restrictive design rules such as fixed width/pitch/orientation of gate-forming polysilicon features. We have been exploring how design might take advantage of these restrictions, and present some preliminary ideas for how we might reduce the computational cost throughout the back end of the design flow through the post-tapeout data processes while improving quality of results: the reliability of OPC/RET algorithms and the accuracy of models of manufactured products. We also believe that the underlying technology, including simulation and analysis, may be applicable to a variety of approaches to design for manufacturability (DFM).