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ACM SIGARCH Computer Architecture News
RaPiD - Reconfigurable Pipelined Datapath
FPL '96 Proceedings of the 6th International Workshop on Field-Programmable Logic, Smart Applications, New Paradigms and Compilers
A New Bare Die Test Methodology
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Structured ASICs: Opportunities and Challenges
ICCD '03 Proceedings of the 21st International Conference on Computer Design
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Proceedings of the 2004 international symposium on Physical design
Structured ASIC, evolution or revolution?
Proceedings of the 2004 international symposium on Physical design
Proximity Communication and Time
ASYNC '05 Proceedings of the 11th IEEE International Symposium on Asynchronous Circuits and Systems
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ACM SIGARCH Computer Architecture News - Special issue: dasCMP'05
Measuring the gap between FPGAs and ASICs
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
IBM Journal of Research and Development - POWER5 and packaging
The accelerator store: A shared memory framework for accelerator-based systems
ACM Transactions on Architecture and Code Optimization (TACO) - HIPEAC Papers
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We introduce a novel chip fabrication technique called "brick and mortar", in which chips are made from small, pre-fabricated ASIC bricks and bonded in a designer-specified arrangement to an inter-brick communication backbone chip. The goal of brick and mortar assembly is to provide a low-overhead method to produce custom chips, yet with performance that tracks an ASIC more closely than an FPGA. This paper examines the architectural design choices in this chip-design system. These choices include the definition of reasonable bricks, both in functionality and size, as well as the communication interconnect that the I/O cap provides. To do this we synthesize candidate bricks, analyze their area and bandwidth demands, and present an architectural design for the inter-brick communication network. We discuss a sample chip design, a 16-way CMP, and analyze the costs and benefits of designing chips with brick and mortar. We find that this method of producing chips incurs only a small performance loss (8%) compared to a fully custom ASIC, which is significantly less than the degradation seen from other low-overhead chip options, such as FPGAs. Finally, we measure the effect that architectural design decisions have on the behavior of the proposed physical brick assembly technique, fluidic self-assembly.