Markov random field modeling in computer vision
Markov random field modeling in computer vision
NanoFabrics: spatial computing using molecular electronics
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
Carbon nanotube field-effect transistors and logic circuits
Proceedings of the 39th annual Design Automation Conference
Towards nanocomputer architecture
CRPIT '02 Proceedings of the seventh Asia-Pacific conference on Computer systems architecture
A system architecture solution for unreliable nanoelectronic devices
IEEE Transactions on Nanotechnology
Array-based architecture for FET-based, nanoscale electronics
IEEE Transactions on Nanotechnology
Energy Bounds for Fault-Tolerant Nanoscale Designs
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Accurate Reliability Evaluation and Enhancement via Probabilistic Transfer Matrices
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Designing logic circuits for probabilistic computation in the presence of noise
Proceedings of the 42nd annual Design Automation Conference
Optimizing noise-immune nanoscale circuits using principles of Markov random fields
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Computer-aided design for DNA self-assembly: process and applications
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
A signal theory based approach to the statistical analysis of combinatorial nanoelectronic circuits
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Designing MRF based error correcting circuits for memory elements
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Nanocomputing in the presence of defects and faults: a survey
Nano, quantum and molecular computing
Defect tolerance at the end of the roadmap
Nano, quantum and molecular computing
Tools and techniques for evaluating reliability trade-offs for NANO-architectures
Nano, quantum and molecular computing
Probabilistic maximum error modeling for unreliable logic circuits
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Probabilistic system-on-a-chip architectures
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Interactive presentation: Techniques for designing noise-tolerant multi-level combinational circuits
Proceedings of the conference on Design, automation and test in Europe
Towards an ultra-low-power architecture using single-electron tunneling transistors
Proceedings of the 44th annual Design Automation Conference
Probabilistic transfer matrices in symbolic reliability analysis of logic circuits
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Probabilistic decision diagrams for exact probabilistic analysis
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Thermal switching error versus delay tradeoffs in clocked QCA circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Towards a framework for designing applications onto hybrid nano/CMOS fabrics
Microelectronics Journal
Hybrid nanoelectronics: future of computer technology
Journal of Computer Science and Technology
CASES '09 Proceedings of the 2009 international conference on Compilers, architecture, and synthesis for embedded systems
Reliability analysis of logic circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Stochastic computational models for accurate reliability evaluation of logic circuits
Proceedings of the 20th symposium on Great lakes symposium on VLSI
A probabilistic Boolean logic for energy efficient circuit and system design
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Characterization of single-electron tunneling transistors for designing low-power embedded systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
History index of correct computation for fault-tolerant nano-computing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Probabilistic error modeling for nano-domain logic circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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As current silicon-based techniques fast approach their practicallimits, the investigation of nanoscale electronics, devices andsystem architectures becomes a central research priority. It is expectedthat nanoarchitectures will confront devices and interconnectionswith high inherent defect rates, which motivates the searchfor new architectural paradigms.In this paper, we propose a probabilistic-based design methodologyfor designing nanoscale computer architectures based onMarkov Random Fields (MRF). The MRF can express arbitrarylogic circuits and logic operation is achieved by maximizing theprobability of state configurations in the logic network. Maximizingstate probability is equivalent to minimizing a form of energythat depends on neighboring nodes in the network. Once we developa library of elementary logic components, we can link themtogether to build desired architectures based on the belief propagationalgorithm. Belief propagation is a way of organizing theglobal computation of marginal belief in terms of smaller localcomputations. We will illustrate the proposed design methodologywith some elementary logic examples.