Stochastic Neural Computation I: Computational Elements
IEEE Transactions on Computers
A Probabilistic-Based Design Methodology for Nanoscale Computation
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Accurate Reliability Evaluation and Enhancement via Probabilistic Transfer Matrices
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Faults, Error Bounds and Reliability of Nanoelectronic Circuits
ASAP '05 Proceedings of the 2005 IEEE International Conference on Application-Specific Systems, Architecture Processors
Survey of Stochastic Computation on Factor Graphs
ISMVL '07 Proceedings of the 37th International Symposium on Multiple-Valued Logic
Probabilistic Treatment of General Combinational Networks
IEEE Transactions on Computers
Probabilistic decision diagrams for exact probabilistic analysis
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
AFIPS '67 (Spring) Proceedings of the April 18-20, 1967, spring joint computer conference
Stochastic computing elements and systems
AFIPS '67 (Fall) Proceedings of the November 14-16, 1967, fall joint computer conference
A reconfigurable stochastic architecture for highly reliable computing
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Estimation and optimization of reliability of noisy digital circuits
ISQED '09 Proceedings of the 2009 10th International Symposium on Quality of Electronic Design
Reliability analysis of logic circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A system architecture solution for unreliable nanoelectronic devices
IEEE Transactions on Nanotechnology
Survey of Stochastic Computing
ACM Transactions on Embedded Computing Systems (TECS) - Special Section on Probabilistic Embedded Computing
RAG: an efficient reliability analysis of logic circuits on graphics processing units
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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As reliability becomes a major concern with the continuous scaling of CMOS technology, several computational methodologies have been developed for the reliability evaluation of logic circuits. Previous accurate analytical approaches, however, have a computational complexity that generally increases exponentially with the size of a circuit, making the evaluation of large circuits intractable. This paper presents novel computational models based on stochastic computation, in which probabilities are encoded in the statistics of random binary bit streams, for the reliability evaluation of logic circuits. A computational approach using the stochastic computational models (SCMs) accurately determines the reliability of a circuit with its precision only limited by the random fluctuations inherent in the representation of random binary bit streams. The SCM approach has a linear computational complexity and is therefore scalable for use for any large circuits. Our simulation results demonstrate the accuracy and scalability of the SCM approach, and suggest its possible applications in VLSI design.