Stochastic computational models for accurate reliability evaluation of logic circuits
Proceedings of the 20th symposium on Great lakes symposium on VLSI
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Accurate and effective algorithm for estimating the reliability of digital combinational circuits
Proceedings of the 46th Annual Simulation Symposium
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This paper is concerned with faults, error bounds and reliability modeling of nanotechnology-based circuits. First, we briefly review failure mechanisms and fault models in nanoelectronics. Second, reliability functions based on probabilistic models are developed for unreliable logic gates. We then show that fundamental gate error bounds for general probabilistic computation can be derived using the nonlinear mapping functions constructed from the gate models. Finally, an analytical approach is proposed for estimating reliabilities of nanoelectronic circuits. This approach is based on the probabilistic modeling of unreliable logic gates and interconnects. In spite of the approximations used in probabilistic modeling, our study suggests that the proposed approach provides a simple and efficient way to model the reliability of nanoelectronic circuits.