Stochastic computational models for accurate reliability evaluation of logic circuits
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Low power logic for statistical inference
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
Stochastic decoding of turbo codes
IEEE Transactions on Signal Processing
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Stochastic computation is a new alternative approach for iterative computation on factor graphs. In this approach, the information is represented by the statistics of the bit stream which results in simple high-speed hardware implementation of graph-based algorithms. Despite the first purpose of its invention (i.e., low-precision digital circuits), the stochastic representation has recently been shown to be able to provide near-optimal decoding performance for practical Low-Density Parity- Check (LDPC) codes, with respect to Sum-Product Algorithm (SPA). This paper provides a survey of stochastic methods for graph-based iterative decoding, the state-of-the-art and, their possible new applications.