Stochastic Neural Computation I: Computational Elements
IEEE Transactions on Computers
Designing logic circuits for probabilistic computation in the presence of noise
Proceedings of the 42nd annual Design Automation Conference
Energy Aware Computing through Probabilistic Switching: A Study of Limits
IEEE Transactions on Computers
A flexible architecture for precise gamma correction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The synthesis of robust polynomial arithmetic with stochastic logic
Proceedings of the 45th annual Design Automation Conference
Stochastic computational models for accurate reliability evaluation of logic circuits
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Survey of Stochastic Computing
ACM Transactions on Embedded Computing Systems (TECS) - Special Section on Probabilistic Embedded Computing
Binary stochastic implementation of digital logic
Proceedings of the 2014 ACM/SIGDA international symposium on Field-programmable gate arrays
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Mounting concerns over variability, defects and noise motivate a new approach for integrated circuits: the design of stochastic logic, that is to say, digital circuitry that operates on probabilistic signals, and so can cope with errors and uncertainty. Techniques for probabilistic analysis are well established. We advocate a strategy for synthesis. In this paper, we present a reconfigurable architecture that implements the computation of arbitrary continuous functions with stochastic logic. We analyze the sources of error: approximation, quantization, and random fluctuations. We demonstrate the effectiveness of our method on a collection of benchmarks for image processing. Synthesis trials show that our stochastic architecture requires less area than conventional hardware implementations. It achieves a large speed up compared to software conventional implementations. Most importantly, it is much more tolerant of soft errors (bit flips) than these deterministic implementations.