Stochastic Neural Computation I: Computational Elements
IEEE Transactions on Computers
A reconfigurable stochastic architecture for highly reliable computing
Proceedings of the 19th ACM Great Lakes symposium on VLSI
FPGA-Based true random number generation using circuit metastability with adaptive feedback control
CHES'11 Proceedings of the 13th international conference on Cryptographic hardware and embedded systems
Using stochastic computing to implement digital image processing algorithms
ICCD '11 Proceedings of the 2011 IEEE 29th International Conference on Computer Design
Robust Data-Optimized Stochastic Analog-to-Digital Converters
IEEE Transactions on Signal Processing
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Stochastic computing refers to a mode of computation in which numbers are treated as probabilities implemented as 0/1 bit streams, which essentially is a unary encoding scheme. Previous work has shown significant reduction in area and increase in fault tolerance for low to medium resolution values (6-10 bits). However, this comes at very high latency cost. We propose a novel hybrid approach combining traditional binary with unary stochastic encoding, called binary stochastic. Similar to the binary representation, it is a positional number system, but instead of only 0/1 digits, the digits would be fractions. We show how simple logic such as adders and multipliers can be implemented, and then show more complex function implementations such as the gamma correction function and functions such as tanh, absolute and exponentiation using both combinational and sequential binary stochastic logic. Our experiments show significant reduction in latency compared to unary stochastic, while using significantly smaller area compared to binary implementations on FPGAs.