Binary stochastic implementation of digital logic
Proceedings of the 2014 ACM/SIGDA international symposium on Field-programmable gate arrays
| Hi-index | 35.68 |
The majority of analog-to-digital converters (ADCs) are designed without taking into consideration the distribution of input signal. In this correspondence, we present a novel ADC architecture that is optimized for a given input signal's statistics. The new robust data-optimized stochastic flash (RDSF) ADC achieves robustness and high accuracy by employing a) a large number of 1-bit quantizers operating in parallel with an additive noise and b) a novel probability density transform (PDT). We demonstrate the performance gain of the RDSF over the conventional flash ADC using simulations and theoretical analysis