Computer
Accurate Reliability Evaluation and Enhancement via Probabilistic Transfer Matrices
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Probabilistic transfer matrices in symbolic reliability analysis of logic circuits
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Probabilistic decision diagrams for exact probabilistic analysis
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Event-driven gate-level simulation with GP-GPUs
Proceedings of the 46th Annual Design Automation Conference
Reliability analysis of logic circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fault Table Computation on GPUs
Journal of Electronic Testing: Theory and Applications
Stochastic computational models for accurate reliability evaluation of logic circuits
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Efficient fault simulation on many-core processors
Proceedings of the 47th Design Automation Conference
FSimGP^2: An Efficient Fault Simulator with GPGPU
ATS '10 Proceedings of the 2010 19th IEEE Asian Test Symposium
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In this paper, we present RAG, an efficient Reliability Analysis tool based on Graphics processing units (GPU). RAG is a fault injection based parallel stochastic simulator implemented on a state-of-the-art GPU. A two-stage simulation framework is proposed to exploit the high computation efficiency of GPUs. Experimental results demonstrate the accuracy and performance of RAG. An average speedup of 412x and 198x is achieved compared to two state-of-the-art CPU-based approaches for reliability analysis.