Interactive presentation: Techniques for designing noise-tolerant multi-level combinational circuits

Authors:
K. Nepal;R. I. Bahar;J. Mundy;W. R. Patterson;A. Zaslavsky
Affiliations:
Brown University, Providence, RI;Brown University, Providence, RI;Brown University, Providence, RI;Brown University, Providence, RI;Brown University, Providence, RI
Venue:
Proceedings of the conference on Design, automation and test in Europe
Year:
2007

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Abstract

As CMOS technology downscales, higher noise levels, wider threshold variation, and low supply voltage will force designers to contend with high rates of soft logical errors and many defective devices. A probabilistic design framework based on Markov random fields (MRF) has been previously proposed to address dynamic fault and noise vulnerability of ultimate digital CMOS circuitry. The idea is to use additional transistors and feedback loops to achieve significant noise immunity and ensure correct logic operations at low VDD. However, the extra reliability achieved in previously published work came at a cost of high transistor counts. In this paper, we present techniques to reduce the transistor count of larger multi-level combinational circuits built within the MRF framework by using variable sharing, implied dependence and supergates. Using these techniques we show an average reduction of approximately 28% in transistor counts over a range of combinational benchmark circuits built within the MRF framework compared to the best previously published results.