Timing-driven placement for FPGAs
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
VPR: A new packing, placement and routing tool for FPGA research
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
Activity-Sensitive Flip-Flop and Latch Selection for Reduced Energy
ARVLSI '01 Proceedings of the 2001 Conference on Advanced Research in VLSI
A reconfigurable architecture for hybrid CMOS/Nanodevice circuits
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
Hybrid CMOS/nanoelectronic digital circuits: devices, architectures, and design automation
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Cell assignment in hybrid CMOS/nanodevices architecture using Tabu Search
Applied Intelligence
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In this paper we have proposed a recursive method for removing the routing congestion in CMOL FPGA circuits where CMOLCAD tool cannot route them successfully. CMOL FPGA architecture, with T basic cells and a latch cell per tile, uses K basic cells (predefined by user) and a latch cell for logic implementation and (T-K) cells for routing. When the circuit encountered congestion, CMOLCAD tool decreases K to route the circuit. This is a drawback for CMOLCAD tool that cannot route the circuit with predefined K. In proposed method, we keep and rank the placement solutions in some of the last iterations of placement algorithm, according to the cost and use them for routing the circuits with more options. If the routing on the highest priority placement solution has failed, this solution will be removed from ranking and another placement solution will be used according to the ranking. This procedure will be continued until circuit routed without congestion by predefined K. The results show that we can remove 9.7% of congestions by applying the proposed method beside CMOLCAD.