Analysis and design of low-energy flip-flops
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
The optimal logic depth per pipeline stage is 6 to 8 FO4 inverter delays
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Optimizing pipelines for power and performance
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
Optimization of scannable latches for low energy
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
Power-optimal pipelining in deep submicron technology
Proceedings of the 2004 international symposium on Low power electronics and design
Combined circuit and architectural level variable supply-voltage scaling for low power
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A reconfigurable architecture for hybrid CMOS/Nanodevice circuits
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
Activity-sensitive flip-flop and latch selection for reduced energy
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Variability of flip-flop timing at sub-threshold voltages
Proceedings of the 13th international symposium on Low power electronics and design
A high speed analog to digital converter for ultra wide band applications
EUC'07 Proceedings of the 2007 conference on Emerging direction in embedded and ubiquitous computing
Routing congestion removing of CMOL FPGA circuits by a recursive method
MINO'10 Proceedings of the 9th WSEAS international conference on Microelectronics, nanoelectronics, optoelectronics
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This work presents new techniques to evaluate the energy and delay of flip-flop and latch designs and shows that no single existing design performs well across the wide range of operating regimes present in complex systems. We propose the use of a selection of flip-flop and latch designs, each tuned for different activation patterns and speed requirements. We illustrate the use of our technique on a pipelined MIPS processor datapath running SPECint95 benchmarks, where we reduce total flip-flop and latch energy by over 60% without increasing cycle time.