Neuromorphic architectures for nanoelectronic circuits: Research Articles
International Journal of Circuit Theory and Applications - Nanoelectric Circuits
A reconfigurable architecture for hybrid CMOS/Nanodevice circuits
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
Nano Logic Circuits with Spin Wave Bus
ITNG '06 Proceedings of the Third International Conference on Information Technology: New Generations
Hybrid CMOS/nanoelectronic digital circuits: devices, architectures, and design automation
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Defect-tolerant nanoelectronic pattern classifiers: Research Articles
International Journal of Circuit Theory and Applications - Nanoelectronic Circuits
Clocking structures and power analysis for nanomagnet-based logic devices
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Fabrication Variations and Defect Tolerance for Nanomagnet-Based QCA
DFT '08 Proceedings of the 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems
Prospects for the development of digital CMOL circuits
NANOARCH '07 Proceedings of the 2007 IEEE International Symposium on Nanoscale Architectures
CMOL crossnets as pattern classifiers
IWANN'05 Proceedings of the 8th international conference on Artificial Neural Networks: computational Intelligence and Bioinspired Systems
A majority-logic device using an irreversible single-electron box
IEEE Transactions on Nanotechnology
Nanoscale memory elements based on solid-state electrolytes
IEEE Transactions on Nanotechnology
Reconfigurable Hybrid CMOS/Nanodevice Circuits for Image Processing
IEEE Transactions on Nanotechnology
Global Reinforcement Learning in Neural Networks
IEEE Transactions on Neural Networks
Design exploration of hybrid CMOS and memristor circuit by new modified nodal analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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It is well recognized that novel computational models, devices and technologies are needed in order to sustain the remarkable advancement of CMOS-based VLSI circuits and systems. Regardless of the models, devices and technologies, any enhancement/replacement to CMOS must show significant gains in at least one of the key metrics (including speed, power and cost) for at least a subset of application domains currently employing CMOS circuits. In addition, effective defect tolerant techniques are a critical factor for the successful adoption of any new computing device due to the fact that nano-scale structures will have defect rates much higher than today's CMOS chips. The task of identifying application domains that could benefit the most from a new model/device/technology and ensuring that the resultant system meets functional requirements in the presence of defects requires synergistic efforts of physical scientists, and circuit and system design researchers. This paper contains a collection of three contributions-each focusing on one particular emergent technology-presenting a basic introduction on the technologies, some of their unique features in contrast with CMOS, potential application domains for these technologies, and new opportunities that they may bring forward in defect tolerance design. The contributions include both traditional and nontraditional state representations which use either electronic or magnetic interactions.